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Codiode/Problems/Arithmetic

16-bit Arithmetic Barrel Shifter

HardVerilog / SystemVerilogBuild

Digital signal processors rely heavily on arithmetic shifts to perform rapid multiplication and division by powers of two while preserving two's complement sign representation. A barrel shifter computes arbitrary shift amounts in a single combinational path, avoiding the latency of sequential shifting. This module accepts a 16-bit input and shifts it left or right by 0 to 15 positions based on a 4-bit shift amount.

When shifting right, the operation can be either logical or arithmetic. A logical right shift pads the most significant bits with zeros. An arithmetic right shift pads the most significant bits with the original sign bit (the most significant bit of the input) to preserve the sign of two's complement numbers. Left shifts always pad the least significant bits with zeros, regardless of the arithmetic flag. The design must compute the result combinationally.

| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | data_in | input | 16 | Input data word to be shifted. | | shift_amt | input | 4 | Number of bit positions to shift (0 to 15). | | dir | input | 1 | Shift direction; 0 indicates left shift, 1 indicates right shift. | | arith_flag | input | 1 | Shift type; 0 indicates logical shift, 1 indicates arithmetic shift. Applies to right shifts only. | | data_out | output | 16 | Shifted result. Purely combinational output. |

Constraints

  • The design must be purely combinational. No clocks, resets, or sequential logic are permitted.
  • Do not use sequential loops that require multiple clock cycles to evaluate.
  • When dir is 0 (left shift), the arith_flag must be ignored, and the least significant bits must be padded with zeros.
  • When dir is 1 (right shift) and arith_flag is 1, the replicated sign bit must match data_in[15].
  • Shift amounts range from 0 to 15; no saturation logic is required for over-shifting.

Topics

Combinational LogicDatapathDSP

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