Signed versus Unsigned Comparison ALU
Branch prediction and control flow units in microprocessors rely on accurate magnitude comparisons to determine execution paths. Using unsigned comparators for signed data leads to catastrophic logical errors in control flow, such as treating a negative offset as a massive positive address.
This module computes greater than and equality comparisons for both signed and unsigned 8-bit integers. To minimize silicon area, the design must compute these comparisons using only a single subtractor and logical flag checks (Zero, Negative, Overflow, and Borrow). The module takes two 8-bit operands, a and b, and produces three boolean flags: sgt (signed greater than), ugt (unsigned greater than), and eq (equal).
The circuit is purely combinational. There is no clock or reset signal. Output ports must reflect the current inputs immediately and must not be registered.
| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | a | input | 8 | First operand; purely combinational | | b | input | 8 | Second operand; purely combinational | | sgt | output | 1 | Active-high signed greater than flag; 1 if a > b | | ugt | output | 1 | Active-high unsigned greater than flag; 1 if a > b | | eq | output | 1 | Active-high equality flag; 1 if a == b |
Constraints
- The circuit is purely combinational; outputs must not be registered.
- Input bit widths are exactly 8 bits; output bit widths are exactly 1 bit.
- The design must derive all outputs from a single subtraction operation.
- Do not use the built-in Verilog comparison operators to solve the core logic; construct the outputs using the subtractor condition flags.
Topics
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Write the module in Verilog, SystemVerilog or VHDL. Your submission is compiled and simulated against a real testbench — you get the waveform back, not a stored answer.
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