8-bit Signed Accumulator

Digital signal processors and audio filters rely on accumulators to integrate data streams over time. If an accumulator wraps around its maximum bound, the resulting mathematical error introduces catastrophic noise or instability into the system. To prevent this, datapath accumulators must detect boundary crossings immediately, halt further accumulation, and flag the error to the control unit.

The solution module receives an 8-bit signed two's complement input and adds it to an internal running total. When the enable signal is asserted, the accumulator updates its value on every clock cycle. If an addition operation causes the running total to exceed the 8-bit signed maximum (127) or fall below the minimum (-128), the module must saturate the output to that boundary value and assert an overflow flag. Once the overflow flag is asserted, it is sticky; the accumulator ignores all further inputs, holding both the saturated value and the overflow flag indefinitely until a system reset occurs.

The module operates on the positive edge of the clock and uses an asynchronous active-low reset. On reset, the accumulator value and the overflow flag must both clear to zero. When the enable signal is low, the accumulator holds its current value and ignores the data input.

### Worked Trace Cycle 1: rst_n=0 → accum_out=0, overflow=0 Cycle 2: rst_n=1, en=1, data_in=100 → accum_out=100, overflow=0 Cycle 3: en=1, data_in=20 → accum_out=120, overflow=0 Cycle 4: en=1, data_in=10 → accum_out=127, overflow=1 (120+10 = 130, exceeds 127) Cycle 5: en=1, data_in=-50 → accum_out=127, overflow=1 (sticky flag ignores new input) Cycle 6: en=0, data_in=0 → accum_out=127, overflow=1 (holds state)

Timing Diagram

{ "signal": [
  { "name": "clk",       "wave": "p......" },
  { "name": "rst_n",     "wave": "01....." },
  { "name": "en",        "wave": "01...0." },
  { "name": "data_in",   "wave": "x====x.", "data": ["100", "20", "10", "-50"] },
  {},
  { "name": "accum_out", "wave": "======.", "data": ["0", "100", "120", "127", "127", "127"] },
  { "name": "overflow",  "wave": "0...1.." }
], "head": { "text": "Accumulation, positive saturation, and sticky overflow." } }

### Port Table | Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | clk | input | 1 | Positive-edge triggered clock | | rst_n | input | 1 | Asynchronous active-low reset; clears accum_out and overflow to 0 | | en | input | 1 | Enable signal; accumulation occurs on posedge clk when 1 | | data_in | input | 8 | Signed two's complement input data | | accum_out | output | 8 | Signed two's complement running total; saturates on overflow | | overflow | output | 1 | Sticky overflow flag; asserts to 1 on boundary crossing |

Constraints

• Clock is positive-edge triggered and reset is asynchronous active-low.
• Output accum_out must be exactly 0 on reset.
• Output overflow must be exactly 0 on reset.
• If an addition exceeds 127, accum_out must saturate to 127 and overflow must become 1.
• If an addition falls below -128, accum_out must saturate to -128 and overflow must become 1.
• Once overflow is 1, accum_out and overflow must remain unchanged regardless of en or data_in until a reset occurs.
• All arithmetic must be treated as signed two's complement.

Topics

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