Saturating Subtractor
Digital signal processing pipelines often require arithmetic operations that clamp to maximum or minimum representable values rather than overflowing. When calculating errors or deltas between signals, standard two's complement subtraction can catastrophically wrap around if the difference exceeds the available bit width. A saturating subtractor prevents this by detecting overflow and pinning the output to the extreme bounds of the representable range.
The module computes the difference between two 8-bit signed two's complement numbers, specifically a minus b. Because two's complement limits are asymmetric, the maximum positive value is +127 and the minimum negative value is -128. If the true mathematical result of the subtraction is greater than +127, the output must clamp to exactly +127. If the true mathematical result is less than -128, the output must clamp to exactly -128. In all other cases, the output is the exact difference.
This is a purely combinational circuit. There is no clock or reset.
| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | a | input | 8 | Signed two's complement minuend | | b | input | 8 | Signed two's complement subtrahend | | diff | output | 8 | Saturated signed difference |
Constraints
- The circuit must be purely combinational.
- The output must clamp to
8'h7F(+127) upon positive overflow. - The output must clamp to
8'h80(-128) upon negative overflow. - The module must correctly handle the asymmetric nature of 8-bit two's complement bounds.
Topics
Solve this problem
Write the module in Verilog, SystemVerilog or VHDL. Your submission is compiled and simulated against a real testbench — you get the waveform back, not a stored answer.
This problem is part of Codiode Pro. The statement above is free to read.
The circuit builder and code editor need a desktop screen. On a phone, read the problem here and open it on a laptop to solve.