Absolute Value with Bit Growth
Signal processing pipelines often require magnitude calculations of signed data. Due to the asymmetry of two's complement representation, taking the absolute value of the most negative number causes an overflow if the bit width remains unchanged. For an 8-bit signed integer, the representable range is -128 to +127. The absolute value of -128 is +128, which requires at least 9 bits to represent as an unsigned integer.
The module computes the absolute value of an 8-bit signed two's complement input and outputs the result as a 9-bit unsigned integer. This bit growth ensures that the most negative 8-bit value is correctly represented without wrapping or data loss.
This is a purely combinational circuit. There is no clock or reset. The output must reflect the absolute value of the input continuously.
Example evaluations: • Input 8'b00000000 (0) produces output 9'b000000000 (0) • Input 8'b01111111 (127) produces output 9'b00001111111 (127) • Input 8'b11111111 (-1) produces output 9'b000000001 (1) • Input 8'b10000000 (-128) produces output 9'b010000000 (128)
| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | a | input | 8 | Signed two's complement input value | | abs_a | output | 9 | Unsigned absolute value of the input |
Constraints
- Combinational logic only; no sequential elements or latches.
- The input
ais strictly an 8-bit signed two's complement integer. - The output
abs_ais strictly a 9-bit unsigned integer.
Topics
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