Parameterized ALU with Safe Defaults
Arithmetic Logic Units form the execution core of any processor. When an instruction decoder issues an undefined opcode, the ALU must fail safely without inferring unintended state-holding elements. Undefined states in combinational blocks often synthesize into latches, which can destroy timing closure and waste area.
This purely combinational module computes an arithmetic or logical operation based on a 3-bit opcode. The data path width is configurable via a parameter W. If the provided opcode does not match a defined operation, the module must output zero to ensure deterministic behaviour.
| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | a | input | W | First operand | | b | input | W | Second operand | | opcode | input | 3 | Operation selector | | out | output | W | Computation result |
The module must support the following operations: • 3'b000: Addition (a + b) • 3'b001: Subtraction (a - b) • 3'b010: Bitwise AND (a & b) • 3'b011: Bitwise OR (a | b) • 3'b100: Bitwise XOR (a ^ b) • Any other value: Output zero
Constraints
- The module is purely combinational; there is no clock or reset.
- The design must strictly evaluate all 8 possible opcode combinations without inferring latches.
- The parameter
Wmust default to 8. - Arithmetic operations must silently wrap on overflow or underflow.
Topics
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