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Codiode/Problems/Arithmetic

8 bit Basic ALU with Flags

EasyVerilog / SystemVerilogBuild

Processors rely on Arithmetic Logic Units to execute mathematical and logical instructions. Beyond computing the raw result, the ALU must generate status flags that the control unit uses to evaluate conditional branch instructions.

The solution module accepts two 8 bit operands and a 3 bit operation code. It computes an 8 bit result based on the selected operation. Simultaneously, it evaluates the result to produce four status flags: zero, negative, carry, and overflow. The overflow flag specifically monitors signed arithmetic operations to detect when a result exceeds the 8 bit two's complement range; the carry flag indicates unsigned overflow or borrow.

This is a purely combinational circuit. There is no clock or reset. All outputs must reflect the current inputs continuously.

Cycle 1: op=0, a=127, b=1 → result=128, zero=0, negative=1, carry=0, overflow=1 Cycle 2: op=1, a=5, b=10 → result=251, zero=0, negative=1, carry=1, overflow=0

| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | a | input | 8 | First operand | | b | input | 8 | Second operand | | op | input | 3 | Operation code | | result | output | 8 | Computed result | | zero | output | 1 | Asserted if result is exactly 0 | | negative | output | 1 | Asserted if the most significant bit of result is 1 | | carry | output | 1 | Carry out for addition; borrow out for subtraction; 0 for all other operations | | overflow | output | 1 | Signed overflow flag; 0 for all non arithmetic operations |

Constraints

  • The module must be purely combinational.
  • op codes are defined as follows: 0 computes a + b; 1 computes a - b; 2 computes a & b; 3 computes a | b; 4 computes a ^ b; 5 computes ~a; 6 passes a unchanged; 7 passes b unchanged.
  • carry is defined as the unsigned carry out for addition and the unsigned borrow out for subtraction.
  • carry and overflow must be strictly forced to 0 for any operation other than addition and subtraction.

Topics

ALUCombinational LogicFlags

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