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Codiode/Problems/Arithmetic

8-bit Logical Barrel Shifter

MediumVerilog / SystemVerilogBuild

Fast arithmetic and bit manipulation units in microprocessors rely on barrel shifters to shift data by an arbitrary number of bits in a single clock cycle. Traditional shift registers require multiple clock cycles to perform large shifts; a barrel shifter accomplishes the exact same result instantly by routing signals through combinational multiplexing logic. Understanding how shifts map to physical hardware prevents engineers from writing abstract code that synthesizes into massive and inefficient logic clouds.

This module performs a logical left shift on an 8-bit input vector. The shift amount is specified by a 3-bit control signal, allowing shifts from 0 to 7 bit positions. Zeros are shifted into the vacated least significant bits.

The entire shifting operation must be executed using exactly three cascading stages of 2-to-1 multiplexers. Stage 0 applies a shift of 1 position. Stage 1 applies a shift of 2 positions. Stage 2 applies a shift of 4 positions. By selectively enabling these stages based on the shift amount bits, any shift between 0 and 7 can be constructed combinationally.

| Signal | Direction | Width | Description | |---|---|---|---| | data_in | input | 8 | The 8-bit data vector to be shifted. | | shift_amt | input | 3 | The 3-bit shift amount controlling the multiplexer stages. | | data_out | output | 8 | The purely combinational shifted 8-bit result. |

Constraints

  • The module must be entirely combinational logic.
  • The design must be structurally built using exactly three stages of 2-to-1 multiplexers.
  • The use of Verilog shift operators is strictly prohibited.
  • Zeros must be shifted into the vacated least significant bits during a logical left shift.
  • No clock or reset signals are used.

Topics

Combinational LogicMultiplexersDatapath

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