8-bit Combinational Popcount
Error correction codes and neural network accelerators frequently rely on population count operations to determine the number of set bits in a data vector. While a sequential shift-and-count approach takes multiple clock cycles, a combinational popcount provides immediate results. However, a naive chain of additions creates a long critical path that can cause severe routing congestion and limit the maximum operating frequency of the entire system.
The module evaluates an 8-bit input vector and computes the total number of bits set to logic 1. To optimize the critical path delay, the computation should be structured as a parallel hierarchical adder tree. Adjacent bits are first added in pairs to form 2-bit sums; adjacent pairs are then added to form 3-bit sums; and finally, the two halves are added to produce the final 4-bit count.
This circuit is purely combinational. There is no clock or reset signal. The output must reflect the current input continuously.
| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | in_val | input | 8 | The data vector to be evaluated | | pop_count | output | 4 | The total number of bits set to 1 in in_val |
Constraints
- The design must be purely combinational with no sequential logic, clocks, or resets.
- The output width must be 4 bits to accommodate the maximum possible count of 8.
- Intermediate addition stages must be correctly sized to prevent arithmetic overflow.
Topics
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Write the module in Verilog, SystemVerilog or VHDL. Your submission is compiled and simulated against a real testbench — you get the waveform back, not a stored answer.
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