32-bit Leading Zero Counter Tree
Floating-point normalisation, priority scheduling, and fast division algorithms rely on finding the first asserted bit in a wide operand. A flat 32-bit priority encoder creates a long critical path. Structuring the leading zero counter as a logarithmic tree reduces the propagation delay from linear to logarithmic time, which is essential to meet timing in high-frequency datapath design.
The module computes the number of leading zeros in a 32-bit input vector. The count starts from the most significant bit (bit 31) and proceeds downwards. To achieve logarithmic delay, the logic must be structured as a tree. The 32-bit input is conceptually divided into eight 4-bit blocks. Each 4-bit block computes its own leading zero count and a zero-flag. These intermediate results are then combined in successive stages to produce the final 6-bit count.
The circuit is purely combinational. There is no clock or reset. The output must reflect the input continuously.
| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | in | input | 32 | Data vector to be evaluated | | zeros| output | 6 | Number of leading zeros; purely combinational output |
Constraints
- The circuit must be purely combinational
- Do not use a single 32-bit case statement, for loop, or if-else chain
- The logic must be constructed hierarchically using 4-bit leading zero counting blocks
- The output must evaluate to exactly 32 when the input is entirely zero
- Bit 31 is the most significant bit and represents the first bit checked for a zero
Topics
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