Twos Complement Overflow in Subtraction
Arithmetic Logic Units (ALUs) must accurately flag boundary violations when mathematical operations exceed the representable range of the data path. In two's complement arithmetic, subtraction requires distinct overflow detection logic compared to addition. Relying on addition-based overflow logic after converting subtraction to a + (-b) introduces edge-case failures, particularly when the subtrahend is the maximum negative number.
The module computes the difference between an 8-bit signed minuend and an 8-bit signed subtrahend. It evaluates the sign bits of the operands and the result to determine if an overflow occurred. An overflow happens when the subtraction of two numbers with opposite signs produces a result that has the opposite sign of the minuend.
This is a purely combinational circuit. There is no clock or reset.
| Signal | Direction | Width | Description | |---|---|---|---| | a | input | 8 | Minuend in two's complement format | | b | input | 8 | Subtrahend in two's complement format | | diff | output | 8 | Difference a - b in two's complement format | | overflow | output | 1 | Asserted to 1 if the subtraction overflows, 0 otherwise |
Constraints
- The design must be purely combinational with no clock or reset dependencies.
- Operands and outputs are 8-bit two's complement signed integers.
- The valid range for operands and results without overflow is -128 to 127.
- You must derive the overflow flag using the sign bits of the operands and the result directly, rather than converting the operation to an addition.
Topics
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