Signed Sequential Multiplier

HardVerilog / SystemVerilogBuild

Digital signal processors and arithmetic logic units frequently require hardware multipliers for signed two's complement numbers. While standard shift-and-add multipliers are highly area-efficient, they natively support only unsigned integers. Standard shift-and-add fails on negative numbers, requiring either Booth encoding or conditional subtraction on the final step.

A signed sequential multiplier computes the product of two 8-bit numbers by evaluating one bit of the multiplier per clock cycle. For an 8-bit multiplier, the first 7 bits represent positive weights, processed using standard addition and arithmetic right shifts. The final most-significant bit (the sign bit) carries a negative weight in two's complement arithmetic. Therefore, on the final iteration, the multiplicand must be conditionally subtracted from the accumulator rather than added, before the final arithmetic right shift.

Clock edge: posedge clk Reset: Asynchronous, active-low rst_n. On reset, all internal state clears, p becomes 0, and done becomes 0. When start is asserted, the module samples a and b and begins computation. If start is asserted while the multiplier is already computing, it must be ignored. Output done asserts for exactly one clock cycle when the 16-bit result p is valid. p must hold its value until the next computation completes.

Example calculation: a = 3 (8'h03), b = -2 (8'hFE). Expected p = -6 (16'hFFFA). Cycle 1: rst_n=0 → state=IDLE, done=0, p=0 Cycle 2: rst_n=1, start=1, a=8'h03, b=8'hFE → (Setup cycle) Cycle 3: start=0 → state=BUSY, count=0, A=8'h00, Q=8'hFE Cycle 4: Q[0]=0 (add 0) → state=BUSY, count=1, A=8'h00, Q=8'h7F Cycle 5: Q[0]=1 (add 3) → state=BUSY, count=2, A=8'h01, Q=8'hBF (A+3=8'h03, shifted right) Cycle 6: Q[0]=1 (add 3) → state=BUSY, count=3, A=8'h02, Q=8'h5F (A+3=8'h04, shifted right) Cycle 7: Q[0]=1 (add 3) → state=BUSY, count=4, A=8'h02, Q=8'hAF (A+3=8'h05, shifted right) Cycle 8: Q[0]=1 (add 3) → state=BUSY, count=5, A=8'h02, Q=8'hD7 (A+3=8'h05, shifted right) Cycle 9: Q[0]=1 (add 3) → state=BUSY, count=6, A=8'h02, Q=8'hEB (A+3=8'h05, shifted right) Cycle 10: Q[0]=1 (add 3) → state=BUSY, count=7, A=8'h02, Q=8'hF5 (A+3=8'h05, shifted right) Cycle 11: Q[0]=1 (SUBTRACT 3) → state=DONE, count=0, A=8'hFF, Q=8'hFA (A-3=8'hFF, shifted right), done=1, p=16'hFFFA Cycle 12: state=IDLE → done=0, p=16'hFFFA (held until next computation)

{ "signal": [
  { "name": "clk",   "wave": "p..........." },
  { "name": "rst_n", "wave": "01.........." },
  { "name": "start", "wave": "010........." },
  { "name": "state", "wave": "=.=........=" },
  { "name": "done",  "wave": "0.........10" },
  { "name": "p",     "wave": "x.........=." }
],
"head": { "text": "Calculation takes 8 clock cycles in the BUSY state." } }

| Signal | Direction | Width | Description | | :--- | :--- | :--- | :--- | | clk | input | 1 | Positive-edge triggered clock. | | rst_n | input | 1 | Asynchronous active-low reset. All registers and outputs clear to 0. | | start | input | 1 | Asserted for 1 cycle to begin multiplication. Ignored if already computing. | | a | input | 8 | Multiplicand (signed two's complement). | | b | input | 8 | Multiplier (signed two's complement). | | p | output | 16 | 16-bit signed product. Valid when done is 1. Holds value until next completion. | | done | output | 1 | Asserts for exactly 1 cycle when p is valid. |

Constraints

Clock edge: posedge clk.
Reset: Asynchronous, active-low. All outputs and internal state must reset to 0.
If start is asserted while the module is actively computing, it must be completely ignored.
The module must perform exactly 8 shift operations.
On the final shift (cycle 8 of the computation), the multiplicand must be conditionally subtracted instead of added.
The arithmetic right shift must correctly sign-extend the accumulator.
The output done must assert for exactly one clock cycle when the final result is ready.
The output p must hold its value after done de-asserts, until a new calculation overwrites it.

Topics

FSMDatapathMath

Solve this problem

Write the module in Verilog, SystemVerilog or VHDL. Your submission is compiled and simulated against a real testbench — you get the waveform back, not a stored answer.

This problem is part of Codiode Pro. The statement above is free to read.

The circuit builder and code editor need a desktop screen. On a phone, read the problem here and open it on a laptop to solve.

Constraints

Clock edge: posedge clk.
Reset: Asynchronous, active-low. All outputs and internal state must reset to 0.
If start is asserted while the module is actively computing, it must be completely ignored.
The module must perform exactly 8 shift operations.
On the final shift (cycle 8 of the computation), the multiplicand must be conditionally subtracted instead of added.
The arithmetic right shift must correctly sign-extend the accumulator.
The output done must assert for exactly one clock cycle when the final result is ready.
The output p must hold its value after done de-asserts, until a new calculation overwrites it.

Topics

FSMDatapathMath

Solve this problem

Write the module in Verilog, SystemVerilog or VHDL. Your submission is compiled and simulated against a real testbench — you get the waveform back, not a stored answer.

This problem is part of Codiode Pro. The statement above is free to read.

The circuit builder and code editor need a desktop screen. On a phone, read the problem here and open it on a laptop to solve.

Signed Sequential Multiplier

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Signed Sequential Multiplier

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