16-bit Sequential Multiplier

MediumVerilog / SystemVerilogBuild

Combinational multipliers consume massive amounts of logic area, making them unsuitable for low-power or area-constrained ASICs. A sequential shift and add multiplier solves this by reusing a single adder over multiple clock cycles. The module receives a 16-bit multiplicand a and a 16-bit multiplier b when the start signal is asserted. It then computes the 32-bit product over exactly 16 clock cycles.

To minimize flip-flop count, your design must use a single 32-bit shift register to hold both the accumulating product and the shifting multiplier.

| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | clk | input | 1 | Positive-edge triggered clock | | rst_n | input | 1 | Asynchronous active-low reset; resets all outputs and internal state | | start | input | 1 | Pulses high for 1 cycle to begin multiplication | | a | input | 16 | Multiplicand input | | b | input | 16 | Multiplier input | | done | output | 1 | Asserts to 1 when calculation is complete; stays 1 until next start | | p | output | 32 | Product of a and b; valid when done is 1 |

Worked Trace

Cycle 1: rst_n=0 → state=IDLE, done=0, p=0
Cycle 2: rst_n=1, start=1, a=3, b=5 → state=IDLE (inputs registered on next edge)
Cycle 3: start=0 → state=CALC, count=0. Internal 32-bit shift register P is initialized to {16'h0000, 16'h0005}.
Cycle 4: state=CALC, count=1 → P[0] was 1, so a (3) is added to the upper 16 bits and shifted right. P becomes 32'h00018002.
Cycle 5: state=CALC, count=2 → P[0] was 0, so P is shifted right without adding. P becomes 32'h0000C001.
Cycle 18: state=CALC, count=15 → The 16th and final shift completes.
Cycle 19: state=DONE → done=1, p=15 (32'h0000000F).

Timing Diagram

{ "signal": [
  { "name": "clk",   "wave": "p...|..." },
  { "name": "rst_n", "wave": "0111|111" },
  { "name": "start", "wave": "0010|000" },
  { "name": "a",     "wave": "xx==|xxx", "data": ["3", "x"] },
  { "name": "b",     "wave": "xx==|xxx", "data": ["5", "x"] },
  { "name": "state", "wave": "====|===", "data": ["IDLE", "IDLE", "CALC", "CALC", "CALC", "CALC", "DONE"] },
  { "name": "done",  "wave": "0000|001" },
  { "name": "p",     "wave": "==xx|xx=", "data": ["0", "0", "15"] }
], "head": { "text": "Multiplication of 3 and 5 taking 16 clock cycles" } }

Constraints

The module must be triggered on the positive edge of clk.
rst_n is an asynchronous, active-low reset.
On reset, done and p must be driven to 0.
The computation must take exactly 16 clock cycles from the cycle after start is asserted until done is asserted.
If start is asserted while a calculation is already in progress, it must be ignored.
done must remain high after a calculation completes until the next start pulse is received.
Both done and p must be registered outputs.

Topics

ArithmeticDatapathState MachineMulti-cycle

Solve this problem

Write the module in Verilog, SystemVerilog or VHDL. Your submission is compiled and simulated against a real testbench — you get the waveform back, not a stored answer.

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