Combinational Array Multiplier Structurally
High-performance DSP blocks and ALUs cannot rely on generic synthesis for multipliers when area and critical path delay must be tightly controlled. A custom array multiplier exposes the exact summation network, allowing hardware engineers to optimize routing and insert pipeline registers at specific logic depths without trusting a black-box synthesis tool.
This module computes the 8-bit product of two 4-bit unsigned integers using a pure structural array multiplier topology. The multiplication of two 4-bit numbers a and b generates a matrix of 16 partial products, where each partial product bit is the logical AND of a[i] and b[j]. These 16 partial products must be summed using a network of half adders and full adders to produce the final 8-bit product p.
This is a purely combinational circuit. There is no clock and no reset. The output p must reflect the product of a and b immediately following any propagation delay through the adder network.
| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | a | input | 4 | Multiplicand | | b | input | 4 | Multiplier | | p | output | 8 | Product of a and b |
Constraints
- The multiplication operator is strictly forbidden.
- The design must be strictly combinational; no registers, flip-flops, or clocks may be used.
- The output
pmust be valid combinationally based on the current inputsaandb. - You must implement the logic structurally using boolean logic gates (AND, XOR, OR) or by defining and instantiating custom half-adder and full-adder submodules.
Topics
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Write the module in Verilog, SystemVerilog or VHDL. Your submission is compiled and simulated against a real testbench — you get the waveform back, not a stored answer.
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