Q8.8 Truncation with Round Half Up
Digital signal processing pipelines frequently use extended fixed-point representations to maintain precision during intermediate calculations. When down-converting a high-precision Q8.8 value back to an 8-bit integer, simple truncation discards the fractional bits, which introduces a negative DC bias across the signal. To preserve signal integrity, the datapath must apply symmetric or half-up rounding.
This module converts a 16-bit signed Q8.8 fixed-point number into an 8-bit signed integer using round-half-up logic. The Q8.8 format consists of 8 integer bits (bits 15 down to 8) and 8 fractional bits (bits 7 down to 0). If the fractional portion is exactly 0.5 (represented by bit 7 being 1 and bits 6 down to 0 being 0) or greater, the integer portion is rounded up by 1. If the fractional portion is less than 0.5, the integer portion remains unchanged (truncated).
This circuit is purely combinational. There is no clock or reset. Wrap-around behavior is expected if rounding causes an overflow.
Worked Trace: • val_in = 16'h0180 (1.5) → The fractional part is 0.5. Round up. val_out = 8'h02 (2). • val_in = 16'h017F (1.496) → The fractional part is less than 0.5. Truncate. val_out = 8'h01 (1). • val_in = 16'hFF80 (-0.5) → The fractional part is 0.5 (in two's complement, -1 + 0.5 = -0.5). Round up by adding 1 to the integer part -1. val_out = 8'h00 (0). • val_in = 16'hFF7F (-0.504) → The fractional part is less than 0.5. Truncate. val_out = 8'hFF (-1).
| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | val_in | input | 16 | Signed Q8.8 fixed-point input | | val_out | output | 8 | Signed 8-bit integer output rounded half up |
Constraints
- The module must be purely combinational.
val_outmust wrap around using standard two's complement arithmetic if rounding causes an overflow (e.g., rounding up8'h7Fyields8'h80).- No saturation logic is required.
Topics
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