Q8.8 Truncation with Convergent Rounding
Digital signal processing chains frequently accumulate data in high-precision fixed-point formats before truncating the results back to standard bit widths. Standard "round half up" algorithms introduce a positive DC bias over millions of samples because the exact halfway point is always rounded in the same direction. Convergent rounding, also known as round-to-nearest-even, eliminates this bias by rounding halfway values to the nearest even integer.
The convergent_rounder module receives a 16-bit signed Q8.8 fixed-point number, consisting of an 8-bit integer portion (the upper 8 bits) and an 8-bit fractional portion (the lower 8 bits). It computes an 8-bit signed integer output dout with a one-cycle pipeline latency.
When valid_in is asserted, the module evaluates the fractional part of din: • If the fraction is less than 0.5, the integer part is passed through unchanged. • If the fraction is greater than 0.5, the integer part is incremented by 1. • If the fraction is exactly 0.5, the module examines the least significant bit of the integer portion. If the integer is even, it is left unchanged. If the integer is odd, it is incremented to make it even.
| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | clk | input | 1 | Positive-edge triggered clock | | rst_n | input | 1 | Synchronous active-low reset; clears dout and valid_out to 0 | | valid_in | input | 1 | Asserted when din contains a valid sample | | din | input | 16 | 16-bit signed Q8.8 fixed-point input | | valid_out| output | 1 | Asserted when dout contains a valid rounded result | | dout | output | 8 | 8-bit signed integer rounded output |
Constraints
- The module must have exactly one clock cycle of latency.
- Outputs
doutandvalid_outmust be registered on the positive edge ofclk. rst_nis synchronous and active-low.- When
valid_inis 0,valid_outmust be 0 on the following clock cycle, anddoutmust hold its previously computed valid value. - Overflows caused by rounding up the maximum positive value (e.g., 127.5 rounding to 128) should simply wrap around naturally according to standard 8-bit 2's complement arithmetic.
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