Register File with Hardwired Zero

Instruction set architectures like RISC-V and MIPS dedicate a specific architectural register to the constant value zero. This simplifies instruction encoding by eliminating the need for a dedicated zero-immediate instruction and provides a guaranteed null sink for discarded results. The register file is the core memory array that stores all architectural registers for the CPU, allowing the ALU to fetch operands and write back results.

The solution module implements a 32-entry by 32-bit register file with two independent combinational read ports and one synchronous write port. Register 0 (address 5'b00000) is hardwired to zero. Any read from address 0 must immediately return 32'b0. Any write to address 0 must be ignored, preserving the hardwired zero state. Reads from non-zero addresses return the current stored value. Writes to non-zero addresses update the stored value on the next clock edge.

Clocking and reset behave as follows: • The write operation is synchronous and occurs on the positive edge of clk. • The reset rst_n is synchronous and active-low. When rst_n is 0 on a positive clock edge, all writable registers (addresses 1 through 31) are cleared to 0. • Reads are purely combinational. The read data outputs rs1_data and rs2_data must immediately reflect the contents of the registers selected by rs1_addr and rs2_addr. • If a read and a write occur to the same non-zero address in the same cycle, the read must return the old stored value, as the write does not commit until the clock edge.

Worked Trace:

Cycle 1: rst_n=0, we=0, rs1_addr=0 → rs1_data=0
Cycle 2: rst_n=1, we=1, rd_addr=5, rd_data=32'hAA, rs1_addr=0 → rs1_data=0
Cycle 3: rst_n=1, we=1, rd_addr=0, rd_data=32'hFF, rs1_addr=5 → rs1_data=32'hAA
Cycle 4: rst_n=1, we=0, rd_addr=0, rd_data=32'h00, rs1_addr=0 → rs1_data=0

{ "signal": [
  { "name": "clk",      "wave": "p...." },
  { "name": "rst_n",    "wave": "01..." },
  { "name": "we",       "wave": "0110." },
  { "name": "rd_addr",  "wave": "x==x.", "data": ["5", "0"] },
  { "name": "rd_data",  "wave": "x==x.", "data": ["AA", "FF"] },
  { "name": "rs1_addr", "wave": "====.", "data": ["0", "0", "5", "0"] },
  { "name": "rs1_data", "wave": "====.", "data": ["0", "0", "AA", "0"] }
], "head": { "text": "Register file operations showing hardwired zero and normal write/read." } }

| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | clk | input | 1 | Positive-edge triggered clock | | rst_n | input | 1 | Synchronous active-low reset; clears registers 1 to 31 to 0 | | we | input | 1 | Write enable; active-high | | rs1_addr | input | 5 | Read port 1 address | | rs2_addr | input | 5 | Read port 2 address | | rd_addr | input | 5 | Write port address | | rd_data | input | 32 | Data to be written to rd_addr | | rs1_data | output | 32 | Read port 1 data (combinational) | | rs2_data | output | 32 | Read port 2 data (combinational) |

Constraints

• The clock edge is posedge clk.
• The reset is synchronous and active-low.
• When rst_n is asserted (0), all registers from address 1 to 31 must be cleared to 0 on the clock edge.
• Address 0 is hardwired to 0. A read from address 0 must combinationally return 0 regardless of what was previously written to it.
• A write to address 0 must not alter the state of any register.
• Reads are purely combinational; they do not wait for a clock edge.
• Writes are synchronous; they only update the register array on the clock edge.
• If rst_n and we are both active in the same cycle, the reset takes priority and the write is ignored.

Topics

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