Simple Dual Port RAM 1R1W

Data pipelines and FIFOs rely on memory structures that can sustain continuous throughput without structural hazards. A Simple Dual Port RAM (1R1W) provides one dedicated write port and one dedicated read port, allowing simultaneous data enqueuing and dequeuing across different addresses in the same clock cycle.

The module maintains an internal memory array of 16 bytes (8-bit width, 4-bit address). On a positive clock edge, if the write enable is asserted, the data on the write port is stored at the specified write address. Simultaneously, if the read enable is asserted, the data at the read address is sampled and registered to the read data port.

Timing and Reset Rules

• Clock edge: All memory writes and read data updates occur on the positive edge of clk.
• Reset type: rst_n is an asynchronous, active-low reset.
• Reset behavior: Asserting rst_n clears the rdata output register to 0. It does not clear the internal memory array.
• Collision rule: If a read and write occur at the exact same address on the same clock cycle, the read must return the old data (read-before-write behavior).
• Hold behavior: If the read enable re is deasserted (0), the rdata register must hold its previous value.

Worked Trace

Cycle 1: rst_n=0 → rdata=0 Cycle 2: rst_n=1, we=1, waddr=4, wdata=170, re=0 → memory[4] becomes 170, rdata=0 (hold) Cycle 3: we=0, re=1, raddr=4 → rdata updates to 170 Cycle 4: we=1, waddr=4, wdata=187, re=1, raddr=4 → memory[4] becomes 187, rdata updates to 170 (read-before-write) Cycle 5: we=0, re=1, raddr=4 → rdata updates to 187 Cycle 6: we=0, re=0 → rdata remains 187 (hold)

Port Table

| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | clk | input | 1 | Positive-edge triggered clock | | rst_n| input | 1 | Active-low asynchronous reset; clears rdata to 0 | | we | input | 1 | Write enable | | waddr| input | 4 | Write address | | wdata| input | 8 | Write data | | re | input | 1 | Read enable | | raddr| input | 4 | Read address | | rdata| output | 8 | Registered read data output |

Constraints

• The internal memory array must be 16 entries deep and 8 bits wide.
• Simultaneous read and write to the same address must implement read-before-write.
• The memory array contents must not be cleared or altered by rst_n.
• Writes must still successfully execute even if rst_n is asserted (0), provided we is 1.

Topics

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