True Dual Port RAM 2RW
Symmetric multiprocessors and shared memory systems require memory arrays that can be accessed by multiple bus masters simultaneously. A True Dual-Port RAM provides two completely independent access ports, allowing simultaneous read and write operations to the same memory space.
This module implements a 16-word by 8-bit true dual-port RAM. It features two independent ports, Port A and Port B. Each port has its own enable, write enable, address, data input, and data output.
On the positive edge of clk: • If a port's enable (ena or enb) is asserted, that port performs an operation. • If the port's write enable (wea or web) is asserted, the data input is written to the memory location specified by the port's address. • If the port's write enable is de-asserted, the data at the memory location specified by the port's address is read and registered to the port's data output.
| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | clk | input | 1 | Positive-edge triggered clock | | ena | input | 1 | Port A enable | | wea | input | 1 | Port A write enable | | addra| input | 4 | Port A address | | dina | input | 8 | Port A data input | | douta| output | 8 | Port A data output; updates on posedge clk | | enb | input | 1 | Port B enable | | web | input | 1 | Port B write enable | | addrb| input | 4 | Port B address | | dinb | input | 8 | Port B data input | | doutb| output | 8 | Port B data output; updates on posedge clk |
Constraints
- The memory array must be exactly 16 words deep and 8 bits wide.
- All memory locations and output registers (
douta,doutb) must be initialized to 0. - Read-first behavior: If a port reads and writes to the same address on the same clock cycle (or if one port reads an address while the other port writes to it), the read operation must return the OLD data present in the memory before the write occurs.
- Simultaneous writes to the exact same address from both Port A and Port B result in undefined behavior and will not be tested.
- Output registers
doutaanddoutbmust be updated on the positive edge ofclk.
Topics
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