Combinational ROM Initialization
Microcontrollers and bootloaders often require a small set of hardcoded instructions or constants available immediately upon power-up. While simulation environments allow loading memory from external files, synthesis tools often restrict or prohibit file I/O operations. Engineers must therefore implement small lookup tables and initialization sequences using pure combinational logic.
The module implements a purely combinational 16-word by 8-bit Read-Only Memory (ROM). It receives a 5-bit address and outputs the corresponding 8-bit data word. Because the address bus can represent 32 distinct values but the ROM only contains 16 words, any address access beyond the first 16 words must return zero.
The ROM contains the following 16 memory words (in hexadecimal): • Address 0: 8'h11 • Address 1: 8'h22 • Address 2: 8'h33 • Address 3: 8'h44 • Address 4: 8'h55 • Address 5: 8'h66 • Address 6: 8'h77 • Address 7: 8'h88 • Address 8: 8'h99 • Address 9: 8'hAA • Address 10: 8'hBB • Address 11: 8'hCC • Address 12: 8'hDD • Address 13: 8'hEE • Address 14: 8'hFF • Address 15: 8'h0F
Because this is a purely combinational circuit, there is no clock or reset. The output data_out must reflect the data at addr immediately.
Worked trace: Input: addr=5 → Output: data_out=8'h66 Input: addr=15 → Output: data_out=8'h0F Input: addr=16 → Output: data_out=8'h00 (out of bounds) Input: addr=31 → Output: data_out=8'h00 (out of bounds)
| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | addr | input | 5 | Memory address to read | | data_out | output | 8 | Data stored at the requested address; outputs 8'h00 for addresses >= 16 |
Constraints
- The design must be purely combinational.
- No flip-flops or latches may be inferred.
- The default case must explicitly assign
8'h00to prevent latch inference. - Do not use
$readmemhor$readmembsystem tasks.
Topics
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