Forcing a Ripple Carry Adder
Synthesis tools aggressively optimize arithmetic operators. When a designer writes a + b in RTL, the tool typically infers a fast but area-intensive hardware macro like a carry-lookahead adder. In highly area-constrained designs where timing is relaxed, a designer needs a way to force the synthesis tool to build a minimal ripple carry adder instead.
This module computes the 4-bit addition of two input operands and a carry-in bit. To prevent the synthesis tool from inferring a macro block, the addition must be constructed structurally. The circuit consists of four cascaded full adders. The carry-out of bit 0 feeds the carry-in of bit 1, and so on. The addition logic must be written using explicit boolean bitwise operators rather than the arithmetic addition operator.
This is a purely combinational circuit. Changes on any input port propagate directly to the output ports without a clock.
| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | a | input | 4 | First operand | | b | input | 4 | Second operand | | cin | input | 1 | Carry-in bit | | sum | output | 4 | Sum result | | cout | output | 1 | Carry-out bit |
Constraints
- You must not use the
+operator anywhere in your code. - The design must be strictly combinational.
- The module must implement exactly four cascaded full adders using bitwise boolean logic.
Topics
Solve this problem
Write the module in Verilog, SystemVerilog or VHDL. Your submission is compiled and simulated against a real testbench — you get the waveform back, not a stored answer.
This problem is part of Codiode Pro. The statement above is free to read.
The circuit builder and code editor need a desktop screen. On a phone, read the problem here and open it on a laptop to solve.