Full Adder Using Only NAND Gates
Hardware synthesis tools frequently map arithmetic logic down to a standard cell library composed entirely of NAND gates. Verifying a synthesized netlist requires understanding how high-level arithmetic translates into fundamental universal gates.
The circuit must compute the sum and carry-out of three 1-bit inputs: A, B, and Cin.
| A | B | Cin | Sum | Cout | |-----|-----|-------|-------|--------| | 0 | 0 | 0 | 0 | 0 | | 0 | 0 | 1 | 1 | 0 | | 0 | 1 | 0 | 1 | 0 | | 0 | 1 | 1 | 0 | 1 | | 1 | 0 | 0 | 1 | 0 | | 1 | 0 | 1 | 0 | 1 | | 1 | 1 | 0 | 0 | 1 | | 1 | 1 | 1 | 1 | 1 |
Constraints
- Use only 2-input NAND gates.
- Do not use XOR, AND, OR, or NOT gates.
- Implement both
SumandCoutlogic.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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