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Codiode/Problems/Combinational Logic

Function Call Latch

HardLogic CircuitDebug

A synthesized parity function calculates the even parity of a 3-bit input to detect transmission errors.

Expected behavior:

| A | B | C | Parity | |-----|-----|-----|----------| | 0 | 0 | 0 | 0 | | 0 | 0 | 1 | 1 | | 0 | 1 | 0 | 1 | | 0 | 1 | 1 | 0 | | 1 | 0 | 0 | 1 | | 1 | 0 | 1 | 0 | | 1 | 1 | 0 | 0 | | 1 | 1 | 1 | 1 |

Simulation shows Parity = 1 when testing the input A=0, B=0, C=0 immediately after A=0, B=0, C=1. The expected output is 0. The circuit fails to update and retains a previous value for this specific input combination. Inspect the circuit and correct the fault.

Constraints

  • The circuit must be strictly combinational.
  • No feedback loops or state-holding elements are permitted in the final design.

Topics

debuggingsynthesislatches

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Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.

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