Gray Code State Machine
Asynchronous clock domain crossing and low power control paths require state machines where only a single flip flop toggles during any state transition. Standard binary encoding can cause transient glitches if multiple bits flip simultaneously and routing delays differ. Gray code encoding guarantees that exactly one bit changes per transition, eliminating these intermediate glitch states.
The module acts as a four state sequence generator. When enabled, it advances through a 2-bit Gray code sequence. When disabled, it holds its current state. The sequence wraps around continuously as long as the enable remains asserted.
Timing and Reset Rules: • Clock edge: Positive edge triggered clk • Reset type: Asynchronous • Reset polarity: Active low rst_n • Output values on reset: state_out resets to 2'b00 • Priority rules: rst_n has highest priority; when rst_n is 1, en determines if the state advances or holds • Registered output: The state_out port directly outputs the current registered state
Worked Trace: Cycle 1: rst_n=0 → state_out=2'b00 (reset) Cycle 2: rst_n=1, en=1 → state_out=2'b01 (advance) Cycle 3: en=1 → state_out=2'b11 (advance) Cycle 4: en=0 → state_out=2'b11 (hold) Cycle 5: en=1 → state_out=2'b10 (advance) Cycle 6: en=1 → state_out=2'b00 (wrap)
flowchart LR
RESET(( )) -->|reset| S00
S00(["00"]):::out -->|en=1| S01
S00 -->|en=0| S00
S01(["01"]):::out -->|en=1| S11
S01 -->|en=0| S01
S11(["11"]):::out -->|en=1| S10
S11 -->|en=0| S11
S10(["10"]):::out -->|en=1| S00
S10 -->|en=0| S10
classDef out fill:#6C5CE7,stroke:#5B4FE8,color:#fff{ "signal": [
{ "name": "clk", "wave": "p......" },
{ "name": "rst_n", "wave": "01....." },
{ "name": "en", "wave": "01.01.." },
{},
{ "name": "state_out", "wave": "======.", "data": ["00", "01", "11", "11", "10", "00"] }
], "head": { "text": "Gray code state progression with enable." } }| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | clk | input | 1 | Positive edge triggered clock | | rst_n | input | 1 | Asynchronous active low reset; sets state_out to 2'b00 | | en | input | 1 | Enable signal; advances state when 1 | | state_out | output | 2 | Current Gray code state, registered |
Constraints
- Clock edge and reset polarity must be strictly observed
- Output
state_outmust be registered on the positive edge ofclk - The state sequence must strictly follow the 2-bit Gray code: 00, 01, 11, 10
- The state must not change when
enis 0 - Reset must be asynchronous;
state_outmust go to 0 immediately whenrst_nis 0, independent of the clock
Topics
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