Hazard-Free Sum-of-Products for F = AB + BC
A static hazard (also called a glitch) is a momentary incorrect output that occurs when inputs change and signals propagate through the circuit at different speeds. In circuits where the output controls a latch enable, a register load, or a power switch, a glitch can cause incorrect behavior even if the final steady-state output is correct. Hazard elimination is a critical skill in ASIC design, particularly for clock gating cells and asynchronous interface logic.
The function F = AB + BC is a classic example of a circuit with a static-1 hazard. A minimal SOP implementation uses only two product terms: AB and BC. However, when B=1 and A transitions from 1 to 0 while C transitions from 0 to 1 simultaneously, the output can momentarily go to 0 — even though both input states (A=1,B=1,C=0) and (A=0,B=1,C=1) produce F=1. This glitch occurs because the AND gate for AB turns off before the AND gate for BC turns on.
The fix is to add the consensus term AC. The full hazard-free SOP is F = AB + BC + AC. The consensus term AC covers the transition directly: when B=1, A=1, C=1 (which cannot happen if B is the only one changing), but more importantly, when B is changing from 1 to 0 to 1 or any combination, AC ensures the output stays 1 throughout the transition through the AB-to-BC overlap region.
| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | A | input | 1 | First input variable | | B | input | 1 | Second input variable | | C | input | 1 | Third input variable | | F | output | 1 | Hazard-free implementation of AB + BC + AC |
Constraints
- The circuit is purely combinational. No clock or state.
- You must implement all three product terms: AB, BC, and AC. Omitting the consensus term AC produces a circuit with a static-1 hazard even though the steady-state truth table is correct.
- The optimal solution uses 3 AND gates and 2 OR gates (5 components total), implementing F = AND(A,B) OR AND(B,C) OR AND(A,C) with a chain of OR gates.
- The grader checks steady-state outputs only. However, include all three terms to demonstrate correct hazard-free design practice.
Topics
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