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Codiode/Problems/Combinational Logic

Hexadecimal and Octal Literals

EasyVerilog / SystemVerilogBuildFree

Memory mapped I/O devices often require configuration registers to be initialized with specific magic numbers or bit patterns during boot. Hexadecimal is mandatory for reading and writing memory addresses and large data buses, while octal is occasionally used for permission masks. This module acts as a combinational read-only memory that provides these fixed configuration values.

The module takes a 1-bit enable and a 3-bit address, and outputs a 32-bit data word. When the enable is low, the output is driven to zero. When the enable is high, the output must be driven using exact hexadecimal literals for the lower four addresses and exact octal literals for the upper four addresses.

| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | en | input | 1 | Active-high enable; when 0, data outputs 0 | | addr | input | 3 | Address to select the configuration word | | data | output | 32 | Configuration word output |

The mapping of addr to data when en is 1 is as follows: • addr = 0: Hexadecimal literal 32'hA5A5A5A5 • addr = 1: Hexadecimal literal 32'h5A5A5A5A • addr = 2: Hexadecimal literal 32'hDEADBEEF • addr = 3: Hexadecimal literal 32'hCAFEBABE • addr = 4: Octal literal 32'o0755 (which evaluates to 32'h000001ED) • addr = 5: Octal literal 32'o0644 (which evaluates to 32'h000001A4) • addr = 6: Octal literal 32'o0777 (which evaluates to 32'h000001FF) • addr = 7: Octal literal 32'o4321 (which evaluates to 32'h000008D1)

Constraints

  • The module is purely combinational; there is no clock or reset.
  • When en is 0, data must be exactly 32'h00000000.
  • You must use the exact sized hexadecimal and octal literals specified.
  • The output data must be exactly 32 bits wide.

Topics

CombinationalSyntaxMUX

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