Implicit Wire Bug in Datapath
A 2-bit bitwise OR circuit combines status flags from dual redundant sensors to produce a unified 2-bit output Y.
Expected behavior:
| A1 | A0 | B1 | B0 | Y1 | Y0 | |------|------|------|------|------|------| | 0 | 0 | 0 | 0 | 0 | 0 | | 0 | 0 | 0 | 1 | 0 | 1 | | 0 | 0 | 1 | 0 | 1 | 0 | | 0 | 0 | 1 | 1 | 1 | 1 | | 0 | 1 | 0 | 0 | 0 | 1 | | 0 | 1 | 0 | 1 | 0 | 1 | | 0 | 1 | 1 | 0 | 1 | 1 | | 0 | 1 | 1 | 1 | 1 | 1 | | 1 | 0 | 0 | 0 | 1 | 0 | | 1 | 0 | 0 | 1 | 1 | 1 | | 1 | 0 | 1 | 0 | 1 | 0 | | 1 | 0 | 1 | 1 | 1 | 1 | | 1 | 1 | 0 | 0 | 1 | 1 | | 1 | 1 | 0 | 1 | 1 | 1 | | 1 | 1 | 1 | 0 | 1 | 1 | | 1 | 1 | 1 | 1 | 1 | 1 |
A typo in the original hardware description language caused an implicit 1-bit wire declaration, severing the upper bit of the datapath in the synthesized netlist. Simulation shows Y1 = 0 for input A1=1, A0=0, B1=0, B0=0. The output Y1 remains 0 for all inputs. Inspect the circuit and correct the fault.
Constraints
- Do not add additional logic gates.
- Repair the broken connection to restore the full 2-bit datapath.
Topics
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