Intentional Transparent Latch

Clock gating cells and specific analog interfaces often require a transparent latch to hold data stable during the off-phase of a clock without introducing the full cycle latency of a flip-flop. While modern RTL design heavily discourages inferred latches, they are sometimes strictly required for specific timing paths.

A transparent D-latch passes the input d directly to the output q when the enable signal en is high. When en goes low, the output q retains its last value, ignoring any further changes on d.

The latch features an asynchronous, active-low reset rst_n. When rst_n is 0, the output q is immediately forced to 0, regardless of the state of en or d. When rst_n returns to 1, normal latch behaviour resumes.

Step 1: rst_n=0, en=0, d=0 → q=0 (Reset forces output to 0) Step 2: rst_n=1, en=1, d=1 → q=1 (Transparent mode, q follows d) Step 3: rst_n=1, en=0, d=0 → q=1 (Latched mode, q holds previous value) Step 4: rst_n=1, en=1, d=0 → q=0 (Transparent mode, q follows d)

{ "signal": [
  { "name": "rst_n", "wave": "01........." },
  { "name": "en",    "wave": "0.1.0..1.0." },
  { "name": "d",     "wave": "0.1.0.10.1." },
  {},
  { "name": "q",     "wave": "0.1....0..." }
], "head": { "text": "Transparent latch operation with asynchronous reset." } }

| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | en | input | 1 | Latch enable; transparent when 1, latches when 0 | | rst_n| input | 1 | Asynchronous active-low reset; drives q to 0 when asserted | | d | input | 1 | Data input | | q | output | 1 | Latch output; resets to 0 |

Constraints

• Must infer a latch, not a flip-flop. Do not use edge-triggered constructs (always_ff, posedge, or negedge).
• Output q must immediately reflect d when en is 1.
• Output q must hold its state when en is 0.
• Asynchronous reset rst_n takes priority over en and d.
• Output q must immediately go to 0 when rst_n is 0.

Topics

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