Late Arriving Signal Optimization

High-speed network routers often merge data from multiple ingress queues into a single egress port. Queues are granted access based on strict priority. However, some queues (like a low-priority debug or telemetry queue) might be sourced from a distant physical partition on the die. If this late-arriving signal is placed at the bottom of a standard priority evaluation chain, the accumulated logic delay will cause setup time violations and prevent the chip from achieving its target clock frequency.

The module late_priority_mux receives four data streams and four request signals. It must output the data associated with the highest-priority request. The priority order is req_a (highest), req_b, req_c, and req_late (lowest). If no request is asserted, the output must be zero.

Because req_late and data_late arrive significantly later than the other signals, they are the critical path. To meet timing closure, you must structure your RTL so that the late-arriving signals bypass the deep logic chain created by the higher-priority early signals. The final synthesis netlist must evaluate the late signal in the very last multiplexer stage before the output.

| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | req_a | input | 1 | Highest priority request; arrives early | | req_b | input | 1 | Second priority request; arrives early | | req_c | input | 1 | Third priority request; arrives early | | req_late | input | 1 | Lowest priority request; arrives late | | data_a | input | 8 | Data for request A; arrives early | | data_b | input | 8 | Data for request B; arrives early | | data_c | input | 8 | Data for request C; arrives early | | data_late | input | 8 | Data for late request; arrives late | | out_data | output | 8 | Selected data; defaults to 8'h00 if no request is active |

Constraints

• The module must be purely combinational; do not use any flip-flops or clocks.
• The logical behavior must exactly match a strict priority encoder (req_a > req_b > req_c > req_late).
• The structural critical path for req_late and data_late must not exceed one 2-to-1 multiplexer delay.
• If multiple early requests are asserted simultaneously, the highest priority request must win.
• If an early request and the late request are asserted simultaneously, the early request must win.

Topics

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