Logarithmic Barrel Shifter Left
High-performance ALUs and memory alignment units require fast, wide data shifts without consuming massive silicon area. The logarithmic barrel shifter achieves this by cascading multiplexer stages based on the binary weight of the shift control signal.
The circuit performs a 4-bit logical left shift on data inputs D3, D2, D1, and D0 by the amount specified by S1 and S0. Zeros must be shifted into the lower bits.
| S1 | S0 | Y3 | Y2 | Y1 | Y0 | |------|------|------|------|------|------| | 0 | 0 | D3 | D2 | D1 | D0 | | 0 | 1 | D2 | D1 | D0 | 0 | | 1 | 0 | D1 | D0 | 0 | 0 | | 1 | 1 | D0 | 0 | 0 | 0 |
Constraints
- Use exactly two stages of 2-to-1 multiplexers.
- Do not use sequential elements or clock signals.
- Do not use N-to-1 multiplexers wider than 2-to-1.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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