Logic Duplication vs Sharing
Hardware synthesis tools are highly capable of optimizing combinational logic. When a complex intermediate calculation is required by multiple downstream paths, writing the equation repeatedly or explicitly defining an intermediate wire both result in the same synthesized hardware, as the tool merges equivalent logic trees.
The module receives an 8-bit input and computes a shared intermediate hash. The hash is defined as the input multiplied by 13 (decimal), XORed with the hexadecimal value 8'hCA. The module then drives two separate 8-bit outputs based on this shared hash. The first output adds 5 (decimal) to the hash. The second output subtracts 5 (decimal) from the hash.
This circuit is purely combinational. There is no clock and no reset. All arithmetic operations wrap around naturally within their 8-bit widths (modulo-256).
Example evaluation trace: • data_in = 8'd2 • Intermediate hash = (2 * 13) ^ 8'hCA = 26 ^ 202 = 8'h1A ^ 8'hCA = 8'hD0 = 208 • hash_out_1 = 208 + 5 = 213 • hash_out_2 = 208 - 5 = 203
| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | data_in | input | 8 | The raw input data to be hashed | | hash_out_1 | output | 8 | The intermediate hash plus 5 | | hash_out_2 | output | 8 | The intermediate hash minus 5 |
Constraints
- The circuit must be purely combinational; no flip-flops or latches are permitted.
- All arithmetic logic must rely on standard 8-bit overflow and underflow behaviour.
- The multiplication factor is strictly 13 (decimal).
- The XOR mask is strictly
8'hCA.
Topics
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