Logical versus Bitwise Operator Synthesis
An address masking unit applies a hardware mask to an incoming memory address bus to clear specific bits for memory alignment.
Expected behavior:
The 4-bit output Out must equal the bitwise AND of the 4-bit Addr and the 4-bit Mask.
| Addr | Mask | Out | |--------|--------|-------| | 15 | 15 | 15 | | 10 | 10 | 10 | | 7 | 2 | 2 | | 10 | 5 | 0 | | 2 | 4 | 0 |
Simulation shows Out = 1 for input Addr = 10, Mask = 5. The masking output is incorrect for mutually exclusive bit patterns. Inspect the circuit and correct the fault.
Constraints
- Do not modify the input or output port definitions or widths.
- The circuit must support full 4-bit width masking.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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