Macro Expansion Latch
A data routing block applies a mode-dependent transformation to an input signal and passes it to the output when enabled.
Expected behavior:
| En | Mode | DataIn | DataOut | |------|--------|----------|-----------| | 0 | 0 | 0 | 0 | | 0 | 0 | 1 | 0 | | 0 | 1 | 0 | 0 | | 0 | 1 | 1 | 0 | | 1 | 0 | 0 | 1 | | 1 | 0 | 1 | 0 | | 1 | 1 | 0 | 0 | | 1 | 1 | 1 | 1 |
Simulation shows DataOut = 1 for inputs En=0, Mode=1, DataIn=1 immediately following a cycle where En=1. The output fails to clear to 0 when the enable signal is deasserted. Inspect the code and correct the fault.
Constraints
- The design must remain purely combinational with no inferred latches
- You must fix the macro expansion logic rather than hardcoding the output
Topics
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Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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