Mealy Output Glitch Detection
Mealy state machines reduce state count by routing asynchronous inputs directly into the output combinational logic. The provided scenario describes a Mealy machine driven by a clock signal clk. The machine has a continuous, asynchronous input x, a current state register S, and an output y. The combinational output logic is defined by the Boolean expression y = S & x. The state S updates only on the rising edge of clk.
Analyze the timing behavior of this architecture. Determine the exact conditions where an asynchronous change in x causes a false positive glitch on y before the clock edge can register a new state.
Constraints
- Assume zero propagation delay through the combinational logic for
yunless specified otherwise. - The state
Sonly transitions on the rising edge ofclk. - The input
xcan toggle at any point during the clock cycle.
Topics
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