Min Max Circuit
Hardware sorting networks and non-linear median filters rely heavily on compare-and-swap primitives. These primitives take two values and route the smaller to one output and the larger to another, forming the fundamental building blocks of hardware sorting algorithms.
This module computes the minimum and maximum of two 8-bit unsigned integer inputs simultaneously. It routes the smaller of the two inputs to the out_min port and the larger to the out_max port. If the inputs are exactly equal, the outputs simply equal the inputs.
The circuit is purely combinational. There is no clock or reset.
| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | a | input | 8 | First unsigned operand | | b | input | 8 | Second unsigned operand | | out_min | output | 8 | The smaller of a and b | | out_max | output | 8 | The larger of a and b |
Constraints
- The circuit must be purely combinational; do not use any clocked elements.
- Inputs are 8-bit unsigned values.
- To optimize for synthesis area, the design must logically infer exactly one relational comparator block.
- The boolean result of the single comparison must drive the multiplexer select lines for both outputs.
Topics
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Write the module in Verilog, SystemVerilog or VHDL. Your submission is compiled and simulated against a real testbench — you get the waveform back, not a stored answer.
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