Modulo by Power of Two
Hardware synthesis tools can sometimes optimize expensive arithmetic operations, but relying on the synthesizer to optimize a modulo operator is risky and can lead to massive area overhead if inferred as a full hardware divider. When the divisor is a known power of two, the modulo operation simplifies entirely to routing wires.
This module computes the remainder of a 16-bit unsigned input x divided by 32. Because 32 is exactly $2^5$, the remainder is mathematically equivalent to the lowest 5 bits of x. The circuit extracts these bits directly without instantiating any arithmetic logic.
| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | x | input | 16 | The unsigned dividend | | y | output | 5 | The remainder of x modulo 32 |
Constraints
- The design must be purely combinational.
- You must not use the Verilog modulo operator (
%) or division operator (/). - The result
ymust exactly match the mathematical modulo 32 ofx.
Topics
Solve this problem
Write the module in Verilog, SystemVerilog or VHDL. Your submission is compiled and simulated against a real testbench — you get the waveform back, not a stored answer.
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