Multiplication by Non Power of Two
Hardware multipliers consume significant silicon area and power. When an algorithm requires multiplying a variable by a fixed constant, synthesis tools typically optimize the operation into a series of hardwired bit shifts and additions to avoid instantiating a full multiplier block.
This module computes the product of an 8-bit input value multiplied by ten. Rather than relying on the synthesis tool to infer the optimization from a generic multiplication operator, the RTL explicitly constructs the shift and add tree. Because the decimal value ten is equivalent to eight plus two, the output is generated by summing the input shifted left by three with the input shifted left by one.
This circuit is purely combinational. There is no clock and no reset. The output must continuously reflect the evaluated product of the input.
Example evaluation: Input data_in = 5 Shift left by 3 computes 5 × 8 = 40 Shift left by 1 computes 5 × 2 = 10 Summing these partial products yields 40 + 10 = 50 Output data_out = 50
| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | data_in | input | 8 | Unsigned multiplicand | | data_out | output | 12 | Unsigned product of the input multiplied by ten |
Constraints
- The design must be purely combinational.
- You must not use the Verilog
*multiplication operator anywhere in your code. - The output width is 12 bits to safely prevent overflow, as the maximum possible product is 2550.
Topics
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Write the module in Verilog, SystemVerilog or VHDL. Your submission is compiled and simulated against a real testbench — you get the waveform back, not a stored answer.
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