Multiplication Width Expansion
Digital signal processing pipelines and arithmetic logic units frequently perform hardware multiplication operations. When multiplying two integer values, the resulting product requires a bit width equal to the sum of the bit widths of the two operands to guarantee no overflow occurs.
The module takes two 16-bit unsigned integer operands and computes their product. It continuously drives the full 32-bit result to the output port without truncating any bits.
This is a purely combinational circuit. Changes on any input port must immediately reflect on the output port.
| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | a | input | 16 | Unsigned multiplicand | | b | input | 16 | Unsigned multiplier | | prod | output | 32 | Full-width product of a and b |
Constraints
- The module must be purely combinational with no clock or reset dependencies.
- The output
prodmust capture the full 32-bit result to prevent overflow. - Operands
aandbare treated as unsigned integers.
Topics
Solve this problem
Write the module in Verilog, SystemVerilog or VHDL. Your submission is compiled and simulated against a real testbench — you get the waveform back, not a stored answer.
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