Multiplier Input Sharing
Digital signal processors rely heavily on multiply-accumulate units for matrix operations, FIR filters, and dot products. Because hardware multipliers consume significant silicon area and power, efficient datapath design requires reusing a single multiplier for multiple instruction types. Relying on synthesis tools to automatically merge operations by writing separate arithmetic expressions can sometimes fail, resulting in two instantiated hardware multipliers instead of one.
The solution module computes a single-cycle arithmetic result based on a mode control signal. When mode is 0, the datapath performs a standard Multiply-Accumulate operation by multiplying vec_val and coeff, then adding acc_in. When mode is 1, the datapath performs a Scalar Scale operation by multiplying vec_val and scalar. To guarantee that only one multiplier is synthesized, the design must explicitly route the operands through multiplexers into a single shared multiplication operator, followed by a final addition.
| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | mode | input | 1 | Control signal (0 = MAC, 1 = Scale); combinational | | vec_val | input | 8 | Signed vector element; combinational | | coeff | input | 8 | Signed coefficient for MAC; combinational | | scalar | input | 8 | Signed scaling factor; combinational | | acc_in | input | 16 | Signed accumulator input; combinational | | result | output | 17 | Signed computed result; purely combinational, no reset |
Cycle 1: mode=0, vec_val=10, coeff=5, scalar=0, acc_in=100 → result=150 Cycle 2: mode=1, vec_val=-10, coeff=0, scalar=3, acc_in=100 → result=-30 Cycle 3: mode=0, vec_val=127, coeff=127, scalar=0, acc_in=0 → result=16129 Cycle 4: mode=1, vec_val=-128, coeff=0, scalar=-128, acc_in=0 → result=16384
{ "signal": [
{ "name": "mode", "wave": "0101" },
{ "name": "vec_val", "wave": "====", "data": ["10", "-10", "127", "-128"] },
{ "name": "coeff", "wave": "====", "data": ["5", "0", "127", "0"] },
{ "name": "scalar", "wave": "====", "data": ["0", "3", "0", "-128"] },
{ "name": "acc_in", "wave": "====", "data": ["100", "100", "0", "0"] },
{},
{ "name": "result", "wave": "====", "data": ["150", "-30", "16129", "16384"] }
], "head": { "text": "Combinational evaluation across different input scenarios." } }Constraints
- This is a purely combinational circuit; there is no clock or reset.
- All arithmetic must be treated as signed 2's complement.
- The output
resultis a 17-bit signed value to guarantee no overflow can occur during the addition. - You must use exactly one
*multiplication operator in your Verilog code to guarantee resource sharing. Do not write separate multiply expressions for each mode. - When
modeis 1, the addition step must effectively add 0 to the product.
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