Mutually Exclusive Adder Sharing
Adders and multipliers are area-intensive components in ASIC and FPGA designs. When two arithmetic operations are mutually exclusive, multiplexing the inputs into a single shared operator consumes significantly less silicon area than instantiating two separate operators and multiplexing their outputs. Hardware engineers routinely refactor naive RTL to explicitly force synthesis tools to share arithmetic logic.
The module computes one of two sums based on a select signal. When sel is 0, the circuit computes a + b. When sel is 1, the circuit computes c + d.
This is a purely combinational logic circuit. There is no clock or reset. The outputs update continuously based on the inputs.
| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | a | input | 8 | First operand for the first addition operation | | b | input | 8 | Second operand for the first addition operation | | c | input | 8 | First operand for the second addition operation | | d | input | 8 | Second operand for the second addition operation | | sel | input | 1 | Selects the operation; 0 outputs a+b, 1 outputs c+d | | result | output | 9 | The computed sum |
Constraints
- The design must be purely combinational.
- The output
resultmust be 9 bits to accommodate the maximum possible sum of two 8-bit unsigned inputs without overflow. - The RTL code must contain exactly one
+operator. Writingsel ? a + b : c + dinfers two adders before synthesis optimization. You must explicitly multiplex the operands to guarantee a single adder is generated.
Topics
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Write the module in Verilog, SystemVerilog or VHDL. Your submission is compiled and simulated against a real testbench — you get the waveform back, not a stored answer.
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