Nested Ternary Priority Logic

Interrupt controllers and bus arbiters frequently rely on priority encoders to resolve simultaneous requests. When multiple devices demand attention at the exact same time, the system must deterministically grant access to the highest priority device while forcing the others to wait. This inference of priority routing is fundamentally different from parallel multiplexing and is commonly implemented using cascading conditional logic.

The solution module evaluates a 4-bit request bus and determines which active bit holds the highest priority. The most significant bit holds the highest priority, cascading down to the least significant bit. The module outputs a 2-bit code representing the index of the highest active request. A separate valid signal indicates whether any request is currently active.

This is a purely combinational logic circuit. There are no clocks or resets.

| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | req | input | 4 | Active-high request bus. Bit 3 has highest priority; bit 0 has lowest. | | code | output | 2 | Index of the highest active request (3, 2, 1, or 0). Defaults to 0 if no requests are active. | | valid| output | 1 | Asserts high (1) when at least one bit in req is high. |

Constraints

• The design must be purely combinational.
• You must implement the priority routing using continuous assignments (assign) with nested ternary operators (? :).
• Priority order is strictly req[3] > req[2] > req[1] > req[0].
• If multiple requests are asserted simultaneously, the output must reflect the index of the highest priority request.
• If req is exactly 4'b0000, code must default to 2'b00 and valid must evaluate to 1'b0.

Topics

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