NOR-only 2-to-1 Multiplexer
Just as NAND gates are functionally complete, so are NOR gates — any Boolean function can be expressed using NOR alone. In practice, NOR-based logic appears in pass-transistor designs and certain FPGA architectures where NOR is the native primitive. Understanding how to construct basic building blocks like a multiplexer from NOR gates demonstrates the kind of structural reasoning that chip design companies expect from interview candidates.
A 2-to-1 multiplexer selects one of two data inputs and routes it to the output. When the select input SEL is 0, the output Y equals data input A. When SEL is 1, the output Y equals data input B. This behavior is defined by Y = A·SEL' + B·SEL.
| SEL | A | B | Y | |-----|---|---|---| | 0 | 0 | 0 | 0 | | 0 | 0 | 1 | 0 | | 0 | 1 | 0 | 1 | | 0 | 1 | 1 | 1 | | 1 | 0 | 0 | 0 | | 1 | 0 | 1 | 1 | | 1 | 1 | 0 | 0 | | 1 | 1 | 1 | 1 |
The 4-NOR implementation is the classic result. The key structural insight is that NOR(X, Y) gives NOT(X OR Y) = X'Y', which lets you build AND-like terms by first inverting. Specifically, NOR(A, SEL) produces A'·SEL', and NOR(B, NOT_SEL) produces B'·SEL. A final NOR of these two terms, after accounting for the double negation, yields exactly the mux output. Verify that this holds for all 8 input combinations before connecting wires.
| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | A | input | 1 | Data input 0, selected when SEL = 0 | | B | input | 1 | Data input 1, selected when SEL = 1 | | SEL | input | 1 | Select line: 0 routes A, 1 routes B | | Y | output | 1 | Selected output: A when SEL=0, B when SEL=1 |
Constraints
- Only NOR2 gates are allowed. No AND, OR, NOT, NAND, or XOR gates.
- The optimal and expected solution uses exactly 4 NOR2 gates.
- The output must be correct for all 8 combinations of SEL, A, B.
- Connecting a NOR input to itself is allowed and produces NOT of that input.
Topics
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