One Hot Decoding Optimization
High-performance crossbar switches rely on one-hot arbitration to route data with minimal latency. When a synthesis tool knows a select bus is strictly one-hot, it can optimize a complex multiplexer into a shallow tree of parallel logic gates, eliminating slow priority-routing chains.
The module receives four 8-bit data buses and a 4-bit one-hot select bus. When a specific bit of the select bus is asserted, the corresponding data bus is routed to the output. To ensure the synthesis tool generates an optimal parallel structure instead of a priority encoder, the module must strictly implement parallel masking. If multiple select bits are asserted simultaneously, the module must output the bitwise OR of the selected data inputs.
This is a purely combinational circuit. Changes on any input must immediately reflect on the output. There is no clock and no reset.
| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | sel | input | 4 | One-hot select bus; purely combinational | | d0 | input | 8 | Data input 0; routed to output when sel[0] is 1; purely combinational | | d1 | input | 8 | Data input 1; routed to output when sel[1] is 1; purely combinational | | d2 | input | 8 | Data input 2; routed to output when sel[2] is 1; purely combinational | | d3 | input | 8 | Data input 3; routed to output when sel[3] is 1; purely combinational | | out | output | 8 | Selected data output; purely combinational |
Constraints
- Purely combinational logic; no registers or clocking.
- If
selis exactly4'b0000,outmust evaluate to8'h00. - If multiple bits of
selare asserted simultaneously,outmust be the bitwise OR of the selected data inputs. This strictly enforces a parallel logic structure instead of a priority chain.
Topics
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