One-Hot State Decoder
High-performance state machines often represent states using one-hot encoding, where exactly one flip-flop is active at any given time. When interfacing with other systems or debugging, this one-hot state must be compressed back into a dense binary representation. Standard case statements can accidentally infer slow priority-encoder logic if the synthesizer is unsure about overlapping conditions. SystemVerilog's unique case keyword guarantees parallel synthesis by asserting that all specified cases are mutually exclusive.
The module continuously monitors an 8-bit input vector. It decodes this input into a 3-bit binary value corresponding to the active bit index. For example, if bit 3 is high, the binary output is 3. A validation flag must also be generated. This flag asserts high when the input is a valid one-hot value. If the input is not one-hot (meaning all zeros, or multiple bits set simultaneously), the validation flag must be driven low and the binary output must default to zero.
Timing and Reset Rules: • This module is purely combinational logic. • There is no clock or reset signal. • Both outputs must evaluate immediately based on the current input state. • Invalid input conditions must immediately force the outputs to their default safe values.
| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | one_hot_in | input | 8 | The one-hot encoded state vector | | binary_out | output | 3 | The decoded binary index of the active bit (0 to 7) | | valid | output | 1 | Asserts to 1 if exactly one bit of one_hot_in is high; 0 otherwise |
Constraints
- All output values must be evaluated combinationally.
- The design must handle all 256 possible input values safely without inferring latches.
binary_outmust be strictly3'b000whenvalidis0.- The implementation should utilize the
unique caseSystemVerilog construct to guarantee parallel logic synthesis.
Topics
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