Operator Precedence Bug
A comparison circuit checks two pairs of redundant sensor signals to ensure both pairs match. The circuit must output 1 only when input A equals input B, and input C equals input D.
Expected behavior:
| A | B | C | D | Y | |-----|-----|-----|-----|-----| | 0 | 0 | 0 | 0 | 1 | | 0 | 0 | 0 | 1 | 0 | | 0 | 0 | 1 | 0 | 0 | | 0 | 0 | 1 | 1 | 1 | | 0 | 1 | 0 | 0 | 0 | | 0 | 1 | 0 | 1 | 0 | | 0 | 1 | 1 | 0 | 0 | | 0 | 1 | 1 | 1 | 0 | | 1 | 0 | 0 | 0 | 0 | | 1 | 0 | 0 | 1 | 0 | | 1 | 0 | 1 | 0 | 0 | | 1 | 0 | 1 | 1 | 0 | | 1 | 1 | 0 | 0 | 1 | | 1 | 1 | 0 | 1 | 0 | | 1 | 1 | 1 | 0 | 0 | | 1 | 1 | 1 | 1 | 1 |
Simulation shows Y = 0 for input A=0, B=0, C=0, D=0. The output is incorrect. Inspect the circuit and correct the fault.
Constraints
- Maintain the intended architecture of checking pair equalities before combining the results.
- Use standard 2-input logic gates for all operations.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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