Parallel Case Enforcement
High-speed memory controllers often receive requests from multiple independent agents. When the system architecture guarantees that these agents will never assert requests on the exact same cycle, the arbitration logic can be optimized for maximum speed.
The module receives a 4-bit one-hot request vector req. It must compute a 2-bit gnt_id indicating which agent is requesting access, alongside a 1-bit valid signal asserted when any request is present. If a standard case or if chain is used, synthesis tools infer a priority encoder, adding unnecessary gate depth. Using a SystemVerilog unique case statement instructs the synthesizer to build flat, parallel logic, significantly reducing the critical path. The platform synthesis grader will verify that the resulting logic depth matches a parallel multiplexer rather than a cascaded priority chain.
This is a purely combinational circuit. There is no clock or reset. Outputs must reflect the input state immediately.
Trace example: • req=4'b0001 implies gnt_id=0, valid=1 • req=4'b0100 implies gnt_id=2, valid=1 • req=4'b0000 implies gnt_id=0, valid=0
| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | req | input | 4 | One-hot request vector; maximum of one bit will be asserted at any time | | gnt_id | output | 2 | Index of the active request; must be 0 if no request is active | | valid | output | 1 | Asserts to 1 if any bit in req is high; otherwise 0 |
Constraints
- Logic must be purely combinational
gnt_idmust explicitly default to 0 whenvalidis 0 to avoid inferring latches- You must use a
unique casestatement to decode the request vector - The platform backend will run Yosys synthesis to verify that the logic depth strictly matches parallel logic routing
Topics
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