Partial Variable Assignment Latch
A masked data buffer passes four signals to the next stage when enabled and drives zeros when disabled to prevent bus contention.
Expected behavior:
When En = 1, outputs Out3, Out2, Out1, and Out0 exactly match inputs In3, In2, In1, and In0. When En = 0, all four outputs must be 0.
Simulation shows Out0 = 1 during a test cycle where En = 0. The output Out0 fails to clear to 0 and is instead retaining its state from the previous cycle. Inspect the circuit and correct the fault.
Constraints
- The fixed circuit must be purely combinational.
- Do not add any clock signals or sequential logic elements.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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