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Codiode/Problems/Combinational Logic

Priority Routing via If Else

EasyVerilog / SystemVerilogBuild

Microcontrollers often receive multiple interrupt requests simultaneously from different peripherals. A hardware interrupt resolver must determine which request gets immediate CPU attention by enforcing a strict priority hierarchy.

The module evaluates a 4-bit interrupt request bus, where bit 3 represents the highest priority peripheral and bit 0 represents the lowest. It computes a valid signal indicating if any interrupts are pending, and a 2-bit identifier for the highest-priority active interrupt. If multiple interrupts are asserted in the same cycle, the one with the highest priority dictates the identifier output.

This logic is purely combinational. The outputs must update immediately based on the current state of the inputs.

Worked trace: • irq = 4'b0000 → irq_valid = 0, irq_id = 2'b00 (No active interrupts) • irq = 4'b0001 → irq_valid = 1, irq_id = 2'b00 (Lowest priority active) • irq = 4'b0101 → irq_valid = 1, irq_id = 2'b10 (Priority 2 beats priority 0) • irq = 4'b1111 → irq_valid = 1, irq_id = 2'b11 (Priority 3 wins all ties)

| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | irq | input | 4 | Interrupt request bus. Bit 3 is highest priority; bit 0 is lowest. | | irq_valid | output | 1 | Asserted (1) if at least one bit in irq is high; otherwise 0. | | irq_id | output | 2 | Index (0 to 3) of the highest-priority active interrupt. Defaults to 0 when no interrupt is active. |

Constraints

  • The circuit must be purely combinational. Do not infer latches or flip-flops.
  • Strict priority must be enforced: irq[3] > irq[2] > irq[1] > irq[0].
  • When irq is exactly 4'b0000, irq_id must be driven to 2'b00.
  • The irq_valid output must only be high when one or more bits of irq are high.

Topics

CombinationalPriority EncoderIf-Else

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