Programmable Logic Array (2-input, 2-output)
A Programmable Logic Array (PLA) is a two-level logic structure consisting of a programmable AND-plane followed by a programmable OR-plane. Every digital function can be expressed in sum-of-products form, which maps directly onto this AND-OR two-level structure. PLAs were the forerunner of modern FPGAs and PALs — understanding their internal structure is fundamental to any field-programmable logic interview. The key distinction between PLA and PAL is that in a PLA both the AND-plane and OR-plane are programmable, while in a PAL only the AND-plane is programmable and the OR connections are fixed.
This problem asks you to implement a two-input, two-output PLA. The inputs are A and B, and the outputs are F1 and F2. The truth table is:
| A | B | F1 | F2 | |---|---|----|----| | 0 | 0 | 1 | 0 | | 0 | 1 | 0 | 1 | | 1 | 0 | 0 | 1 | | 1 | 1 | 1 | 1 |
From inspection: F1 = XNOR(A,B) = A'B' + AB. F2 = XOR(A,B) + AB = A'B + AB' + AB = A + B (OR gate). The minimal SOP expressions are F1 = A'B' + AB and F2 = A + B. The AND-plane computes the product terms: P1 = A'B', P2 = AB, P3 = A, and the OR-plane selects which products feed each output: F1 = P1 + P2, F2 = P3.
An efficient gate-level implementation shares the product terms between outputs. Use NOT gates to generate A' and B'. Compute AND(A',B') for the P1 product term and AND(A,B) for the P2 product term. The output F1 is OR(P1, P2). The output F2 is OR(A, B) directly — since F2 = A + B, no AND term is needed beyond the bare inputs.
| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | A | input | 1 | First input variable | | B | input | 1 | Second input variable | | F1 | output | 1 | First output function: XNOR(A,B) | | F2 | output | 1 | Second output function: OR(A,B) |
Constraints
- The circuit is purely combinational. No clock or state.
- Implement F1 = A'B' + AB (XNOR) and F2 = A + B (OR) using the PLA AND-plane + OR-plane structure.
- The optimal solution uses 2 NOT gates, 2 AND gates, and 2 OR gates (6 components total) when sharing intermediate product terms.
- All 4 input combinations must produce the correct outputs for both F1 and F2.
Topics
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