Register Duplication for Fanout
High fanout nets, such as global control signals or enables, often cause timing violations in large ASIC and FPGA designs. A single flip-flop driving thousands of endpoints physically cannot transition fast enough due to wire capacitance. Hardware engineers resolve this by manually duplicating the source register and distributing the load across multiple equivalent flip-flops.
This module takes a single scalar control input and registers it across four distinct flip-flops. Each flip-flop drives a dedicated output port intended for a separate datapath block. All four outputs transition identically based on the input, but they must be driven by separate registers in the RTL.
The clock edge is posedge clk. The reset is asynchronous and active-low via rst_n. On reset, all four outputs default to 0. On the clock edge, all four outputs latch the current value of ctrl_in.
Cycle 1: rst_n=0 → ctrl_out_0=0, ctrl_out_1=0, ctrl_out_2=0, ctrl_out_3=0 Cycle 2: rst_n=1, ctrl_in=1 → ctrl_out_0=1, ctrl_out_1=1, ctrl_out_2=1, ctrl_out_3=1 Cycle 3: ctrl_in=0 → ctrl_out_0=0, ctrl_out_1=0, ctrl_out_2=0, ctrl_out_3=0 Cycle 4: ctrl_in=1 → ctrl_out_0=1, ctrl_out_1=1, ctrl_out_2=1, ctrl_out_3=1
{ "signal": [
{ "name": "clk", "wave": "p......" },
{ "name": "rst_n", "wave": "01....." },
{ "name": "ctrl_in", "wave": "x1.0.1." },
{},
{ "name": "ctrl_out_0", "wave": "0.1.0.1" },
{ "name": "ctrl_out_1", "wave": "0.1.0.1" },
{ "name": "ctrl_out_2", "wave": "0.1.0.1" },
{ "name": "ctrl_out_3", "wave": "0.1.0.1" }
], "head": { "text": "Register duplication across four output ports." } }| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | clk | input | 1 | Positive-edge triggered clock | | rst_n | input | 1 | Asynchronous active-low reset; all outputs go to 0 when asserted | | ctrl_in | input | 1 | Control signal to be registered | | ctrl_out_0 | output | 1 | Registered control signal for datapath block 0 | | ctrl_out_1 | output | 1 | Registered control signal for datapath block 1 | | ctrl_out_2 | output | 1 | Registered control signal for datapath block 2 | | ctrl_out_3 | output | 1 | Registered control signal for datapath block 3 |
Constraints
- Clock edge must be
posedge clk - Reset must be asynchronous and active-low
- All outputs must initialize to
0on reset - Outputs must be registered; combinatorial pass-through is invalid
Topics
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